Macro catalog

A library of pre-generated SRAM22 macros for SKY130 is published in the sram22_sky130_macros repository. Each macro includes its .gds.gz, .lef, .spice, .v, and multi-corner .lib files — the views consumed by the OpenROAD and Cadence flows.

After downloading, run the repository's ./unzip.sh, or use gzip -d <macro>.gds.gz for an individual layout.

Check the downloaded views before integration: catalog SPICE files can reference external files, and some whole-word-write Verilog models omit the scalar wmask present in LEF/SPICE. Resolve those file references and use a model whose ports match the physical interface.

22 macros · 19 silicon-validated Silicon-validated only

Macro	Words	Width	Mux	Write size	Capacity	Silicon
sram22_64x22m4w22	64	22	4	22	0.172 KiB	—
sram22_64x24m4w8	64	24	4	8	0.188 KiB	✓
sram22_64x32m4w8	64	32	4	8	0.25 KiB	✓
sram22_128x16m4w8	128	16	4	8	0.25 KiB	✓
sram22_128x24m4w8	128	24	4	8	0.375 KiB	✓
sram22_128x32m4w8	128	32	4	8	0.5 KiB	✓
sram22_128x40m4w20	128	40	4	20	0.625 KiB	—
sram22_256x8m8w1	256	8	8	1	0.25 KiB	✓
sram22_256x16m8w8	256	16	8	8	0.5 KiB	✓
sram22_256x32m4w8	256	32	4	8	1 KiB	✓
sram22_256x64m4w8	256	64	4	8	2 KiB	✓
sram22_256x128m4w8	256	128	4	8	4 KiB	✓
sram22_512x8m8w1	512	8	8	1	0.5 KiB	✓
sram22_512x32m4w8	512	32	4	8	2 KiB	✓
sram22_512x64m4w8	512	64	4	8	4 KiB	✓
sram22_512x128m4w8	512	128	4	8	8 KiB	✓
sram22_1024x8m8w1	1024	8	8	1	1 KiB	✓
sram22_1024x32m8w8	1024	32	8	8	4 KiB	✓
sram22_1024x64m4w8	1024	64	4	8	8 KiB	✓
sram22_2048x8m8w1	2048	8	8	1	2 KiB	✓
sram22_2048x32m8w8	2048	32	8	8	8 KiB	✓
sram22_2048x64m8w8	2048	64	8	8	16 KiB	—

Naming

A macro named sram22_DxWmMwG has depth D (words), word width W (bits), column-mux ratio M, and write granularity G (bits). For example, sram22_64x32m4w8 is 64 words × 32 bits, mux ratio 4, byte-masked.

Silicon measurements

The validation report states that the marked macros were taped out via Cadence's shuttle program and measured working at VDD = 1.8 V and a 25 MHz clock.

Generating a macro not listed here

Follow the Quickstart to configure and generate a macro. Characterize its timing and run physical verification for the configuration and process corners used in your design.