Pin list

An SRAM22 macro is a single-port (1RW) synchronous SRAM. On each rising clock edge, when chip-enable is asserted, it performs either a read or a write to one word:

With ce = 1 and we = 0 → read: dout becomes the contents of addr after the clk-to-Q delay.
With ce = 1 and we = 1 → write: din is written to addr, gated by the per-group wmask.
With ce = 0 → idle: the array holds its state and dout is unchanged.

Address, input data, and access controls are sampled on the rising edge of clk. Physical rstb is an asynchronous active-low reset of control state and input flip-flops. It inhibits accesses but does not initialize the memory contents or read output. The behavioral model checks reset at the clock edge and does not model asynchronous internal transitions or analog timing.

Pins

The widths below are parametric. For a macro named sram22_<num_words>x<data_width>m<mux_ratio>w<write_size>:

addr_width = log2(num_words)
wmask_width = data_width / write_size

Pin	Direction	Width	Layer	Purpose
`clk`	input	`1`	met1	Clock. Address, data, and access controls are captured on the rising edge; dout updates after a read. Physical reset is asynchronous.
`rstb`	input	`1`	met1	Asynchronous active-low physical reset of control state and input flops. Inhibits accesses; does not initialize stored memory or dout.
`ce`	input	`1`	met1	Chip enable. When high, a read or write occurs on the rising clock edge; when low, the array is idle and retains data.
`we`	input	`1`	met1	Write enable. With ce high, we=1 performs a write and we=0 performs a read.
`wmask`	input	`wmask_width`	met1	Bit i enables writing data bits [i·write_size +: write_size]. Always present; scalar when write_size equals data_width.
`addr`	input	`addr_width`	met1	Word address, where addr_width = log2(num_words).
`din`	input	`data_width`	met1	Write data input, sampled on the rising edge during a write.
`dout`	output	`data_width`	met1	Read data output. Valid after the clk-to-Q delay following a read; holds until the next read.
`vdd`	inout	`1`	met2	Power supply (1.8 V nominal).
`vss`	inout	`1`	met2	Ground.

Write mask

wmask is always present. When write_size == data_width, it is a scalar whole-word write mask; drive it high to allow writes. Bit i of wmask enables writing data bits [i·write_size +: write_size], so a macro with data_width = 32 and write_size = 8 has a 4-bit mask, one bit per byte.

Power pins

vdd and vss are routed on met2; all signal pins are on met1. The Verilog model exposes vdd/vss only under the USE_POWER_PINS macro.

Verilog declaration

For the sram22_64x32m4w8 macro (64 words × 32 bits, byte write mask):

module sram22_64x32m4w8 (
`ifdef USE_POWER_PINS
  inout  vdd,
  inout  vss,
`endif
  input  clk,
  input  rstb,            // active-low reset
  input  ce,              // chip enable
  input  we,              // write enable
  input  [3:0]  wmask,    // data_width / write_size
  input  [5:0]  addr,     // log2(num_words)
  input  [31:0] din,
  output [31:0] dout
);

Next: see exactly where each pin sits on the layout in Pin positions, or how the pins relate in time in Timing diagrams.

Pins​

Verilog declaration​

Pins

Verilog declaration