Timing diagrams

Address, data, and access controls are captured on the rising clock edge. Physical reset is asynchronous; the behavioral Verilog model checks rstb at the clock edge. Neither reset nor a disabled access initializes the stored data or dout.

Synchronous read then write, with rstb and all wmask bits high (schematic — setup/hold shown exaggerated). Example rising-transition timing at 1.8 V, 25 °C (PVT_1P8V_25C). Clock and input slew are 0.002 ns; output load is 0.007 pF. Full rise/fall constraints are in the .lib; see Waveforms for the physical bitline behavior.

With rstb = 1 and ce = 1, we = 0 reads and we = 1 writes. A read updates dout after the internal access delay; a write changes only the groups enabled by wmask. Each input must meet its own rise/fall setup and hold constraints. The diagram is not to scale and omits reset and mask traces for clarity.

Characterized constraints

These values come from the published Liberty file for sram22_64x32m4w8 at 1.8 V, 25 °C (PVT_1P8V_25C). Each range spans every entry of the corresponding rise- or fall-constraint table, including both slew axes. “Rise/fall” below refers to the input transition; all these setup/hold arcs are relative to a rising clock edge. Use the full Liberty tables and the actual signal slews in STA.

Input	Setup, rising (ns)	Setup, falling (ns)	Hold, rising (ns)	Hold, falling (ns)
addr	0.1334–0.2084	0.2076–0.3294	0.0738–0.1173	0.0732–0.1178
ce	0.1334–0.2082	0.2074–0.3291	0.0733–0.1169	0.0728–0.1174
din	0.1243–0.1968	0.1933–0.3143	0.0880–0.1299	0.0882–0.1304
rstb	0.1411–0.2024	0.1904–0.2951	0.0819–0.1240	4.3009–4.3649
we	0.1334–0.2082	0.2075–0.3292	0.0735–0.1171	0.0729–0.1175
wmask	0.1276–0.2009	0.1970–0.3184	0.0792–0.1218	0.0785–0.1221

Reset timing

The published library has a notably larger falling-transition reset hold constraint: 4.3009–4.3649 ns. Preserve it in timing analysis.

Quantity	Table range (ns)
Clock high pulse width constraint	0.1897–0.2394
Clock low pulse width constraint	0.2624–0.3120
Minimum period, rising clock constraint	2.7495–2.7497
Minimum period, falling clock constraint	2.7495–2.7497
Clock-to-Q, rising output	3.0116–4.3918
Clock-to-Q, falling output	3.0441–3.9225

Choose the clock period using the minimum-period constraint together with output load, downstream setup time, clock skew, and the other constraints on each path.

Internal sequence

The clock pulse disables precharge and sense enable, then enables the gated row-address path. Replica bitline detection ends the read wordline-enable pulse; a decoder-replica delay sequences sensing and subsequent precharge. The output is retained by a differential latch. See Algorithms for the implementation and Waveforms for an illustrative main-bitline plot.