Algorithms

SRAM22 assembles fixed bitcell and sense-amplifier macros with parameterized peripheral circuits. The implementation lives in src/blocks/.

Generation pipeline

1. Derive rows, columns, address widths, and write-mask groups from the configuration.
2. Size decoder/driver stages and scale precharge, transmission-gate mux, and write-driver devices.
3. Assemble the schematic and layout, including fixed bitcells and sense amplifiers.
4. Write GDS, LEF, SPICE, behavioral Verilog, and interpolated Liberty timing.
5. Optionally run licensed verification and Liberty characterization with a BWRC build.

Decoder sizing

The row-address bits and their complements are captured in input flip-flops. wlen gates both polarities of these inputs before the row decoder. The hierarchical decoder combines them into one selected wordline and drives its load through sized gate stages.

Conceptual signal flow: wlen gates registered row-address inputs before decoding. Driver stages are part of the sized decoder tree; their effective wordline load is capped at 500 fF for sizing.

The generator estimates wordline capacitance as:

C_wordline = (columns + 4) × WORDLINE_CAP_PER_CELL × 1.5

The extra cells and safety factor are part of the sizing model. The effective load is capped at WORDLINE_CAP_MAX = 500e-15 F. Stage count and sizes are estimated using logical effort and RC gate models. The cap limits further scaling when routing parasitics are expected to dominate.

Address partitioning uses balanced two- or three-way splits. The top-level split is two-way, and smaller groups terminate in two- or three-input decode gates.

Self-timed control

The controller creates an internal pulse from a delayed clock qualified by the registered chip-enable signal. Active-low SR latches and delay chains sequence precharge, wordline enable, sense enable, and write-driver enable.

During a read:

1. The clock pulse resets sense enable and drives pc_b high to disable precharge.
2. A delayed pulse sets wordline enable and drives the replica wordline.
3. The replica bitline discharges. An inverter detects its transition; the actual trip voltage depends on the device characteristics and operating conditions.
4. Replica detection resets wordline enable. A decoder-replica delay then sequences sense-amplifier activation after the wordline-reset event.
5. An additional delay re-enables precharge by driving pc_b low.

During a write, a delayed clock pulse selects the wordline-reset event instead of replica detection. Write-driver enable is set for a write and reset after the replica-decoder delay. Precharge is subsequently restored. The write mask qualifies the write-driver groups.

The decoder replica delays the end-of-access sequence. The precharge latch's q output is pc, and its complemented output drives pc_b.

Replica timing is intended to track array behavior. Adequate sensing margin and write completion still need verification for each configuration and PVT range. See Waveforms for an illustrative simulated read.

Array organization

SRAM22 has one bitcell array. Every row shares a wordline, and every column shares a bl/br pair across its rows. A decoder sits to the left and column peripherals below the array.

Column circuitry and the mux ratio

For mux ratio M, the array has num_words / M rows and data_width × M columns. The low log2(M) address bits select one of M bitline pairs through transmission-gate muxes. Each data bit has a shared sense amplifier, write driver, and differential output latch. Input data and write-mask bits use flip-flops.

Increasing M reduces the number of rows and the bitline load while increasing the number of cells across a wordline. This makes the array wider and shorter and increases mux overhead. SRAM22 supports M=4 and M=8, with at least 16 rows and 16 columns.

write_size sets the number of data bits controlled by each mask bit. A whole-word write still has a scalar wmask; drive it high to permit writes.