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Documentation

SRAM22 is a configurable SRAM generator developed at UC Berkeley. Given a short TOML description — depth, word width, column-mux ratio, and write granularity — it parametrically generates an SRAM macro for the SkyWater SKY130 open process.

The generator emits these views:

  • GDS layout
  • LEF abstract (for place-and-route)
  • SPICE netlist
  • Verilog behavioral model
  • Liberty timing at TT, SS, and FF (interpolated by default)

The quickstart describes the interpolation model's supported configurations and optional commercial characterization. Run DRC/LVS and timing checks for your generated configuration and integration.

Architecture at a glance​

SRAM22 builds a self-timed SRAM around one 6T bitcell array with shared column peripherals and replica-based timing control. Address, data, and access controls are captured on the rising clock edge. Physical reset is asynchronous. Replica bitline detection ends the read wordline pulse, followed by delayed sensing and precharge. The output uses a differential latch.

SRAM22 block diagram: registered row addresses feed predecoders and the row decoder; column addresses select column muxes. Timing control sequences the array and column circuitry, which receives registered data and write masks.
Top-level organization. M = mux ratio, D = depth, W = word width, G = write-mask granularity. Number of rows R = D / M; number of columns C = W · M.

Where to go next​

QuickstartInstall SRAM22 and generate your first SRAM.OpenROAD tutorialIntegrate a macro into an open-source OpenROAD flow.Cadence tutorialUse a macro in a Genus / Innovus flow.InterfacePins, physical pin positions, and timing.InternalsWaveforms, layout browser, and the sizing algorithms.Macro catalogDownload pre-built layouts and timing libraries.